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Archive for the Category: Phase-Locked Loops (PLL)
My article in Microwaves & RF finally hit. The web version has a lot of typos in it, however, so you will probably find the PDF version a lot easier read. Follow this link and you’ll see the file link. Thanks for your interest.
I have a feature design article that is to be published in the May issue of Microwaves & RF. After it runs, I will post a copy of the complete article in PDF format for easier reading. The article presents several nonconventional methods that can help with demanding PLL designs.
James A Crawford Having reached a sufficient station in life that I have either heard most of the typical interview questions that might come my own direction, or have the wit and nonsense to navigate my way through something that I don’t know and talk about the weather or something completely unrelated, this on-going collection […]
Abstract The need frequently arises to design a discrete-time digital signal processing (DSP) algorithm that closely mimics a conventional continuous-time phase-locked loop (CTPLL). Similarly, it is often desirable to talk about the DSP implementation in terms of traditional quantities like damping factor and equivalent noise bandwidth. This memorandum examines this interplay between discrete and continuous […]
This topic comes up rather frequently. I have addressed this in a lot of detail in a paper titled “Digital Redesign of Analog Phase-Locked Loops” and it is available on this site under the PLL section. You will need to sign-up, however, to gain access to this article that appears on the “Subscription Papers” tab.
The minimum acceptable gain- and phase-margin depends upon your application of course. Phase margin is generally more critical unless wide variations in loop-gain are expected (due to large changes in the feedback divider ratio, VCO tuning sensitivity, or equivalent). Small phase margin always leads to (i) phase noise peaking in the frequency domain and (ii) […]