Microwaves May 2011 Issue

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Unconventional PLLs Simplify Difficult Designs

(This article was posted here in its entirety in PDF format following publication in the May 2011 issue of Microwaves & RF.)

These four unconventional PLL configurations may be unfamiliar to many high-frequency engineers, but they can add a great deal of flexibility to a synthesizer bag of design tricks.

Modern communications systems rely heavily on a key building block, the phase-lock loop (PLL). PLL design has been covered extensively over the years, but the four techniques described in this article will likely be unfamiliar to most readers. These methods should prove helpful across a wide range of applications, including both analog/RF and digital-signal-processing (DSP) domains.

Technique #1: Addition of a Passive Lag-Lead Network

Readers familiar with PLL design will recognize the classic type-2 fourth-order loop filter shown in Figure 1. This PLL is fourth-order because the single-ended loop filter has three capacitors (C1, C3, and C5) and the voltage-controlled oscillator (VCO) contributes one additional pole.

Focusing first on Figure 1, the phase detector in this case has two outputs that are often labeled as the pulse-up (PU) and pulse-down (PD) outputs. Denoting the phase detector gain by Kd (V / rad. ), the VCO tuning sensitivity by Kv ( rad. / sec. / V ), and assuming that the loop filter component values are perfectly symmetric, the open-loop gain transfer function can be written as

Figure 1




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